1. Field of the Invention
The present invention relates to a magnetic detection apparatus that detects the speed of a moving member by using a magnetic sensor element group.
2. Description of the Related Art
For example, there is a scheme in which a bridge circuit is configured by forming electrodes at each terminal of a magnetic reluctance element (magneto-electric transducer), a power source of a constant voltage and a constant current is connected between two electrodes facing each other in the bridge circuit, variation in a resistance value of the magnetic reluctance element is converted into voltage variation, and variation in a magnetic field applied to the magnetic reluctance element is detected (for example, refer to JP-A-2007-192733).
Hereinafter, the conventional magnetic detection apparatus disclosed in JP-A-2007-192733 will be described with reference to the accompanying drawings.
FIGS. 14A and 14B are schematic diagrams illustrating the configuration of a magnetic circuit of the conventional magnetic detection apparatus, wherein FIG. 14A is a perspective view of the magnetic circuit and FIG. 14B is a top view of the magnetic circuit.
In FIGS. 14A and 14B, the conventional magnetic detection apparatus includes a magnet 1 that generates a bias magnetic field, and a processing circuit unit 2 provided on the magnet 1 and having circuits formed on a board. The processing circuit unit 2 includes an IC chip in which magnetic reluctance elements 21a and 21b serving as a magnetic sensor are integrally formed as segments with each other. The magnetic reluctance elements 21a and 21b, for example, are arranged to face a magnetic moving member 3 having protrusions formed at the peripheral edge of a disc to change the magnetic field, and are arranged in parallel to the movement direction of the magnetic moving member 3. Reference numeral 4 indicates a rotating axis of the magnetic moving member 3, the magnetic moving member 3 rotates in synchronization with the rotation of the rotating axis 4, and the resistance values of the magnetic reluctance elements 21a and 21b change according to the displacement of the magnetic moving member 3.
In addition, in FIGS. 14A and 14B, the magnetic reluctance elements 21a and 21b are shown by one black block, respectively. However, magnetic reluctance elements may be arranged to detect predetermined variation in a magnetic field.
FIG. 15 is a circuit configuration diagram illustrating the configuration of a processing circuit unit of the conventional magnetic detection apparatus using magnetic reluctance elements. FIGS. 16 and 17 are timing charts illustrating operation waveforms according to the processing circuits of FIG. 15, wherein FIG. 16 illustrates operation waveforms of each signal when the rotation number of a magnetic moving member 3 is low, and FIG. 17 illustrates operation waveforms of each signal when the rotation number of the magnetic moving member 3 is high.
In FIG. 15, the conventional magnetic detection apparatus includes a bridge circuit 10, a first comparison circuit 31, a second comparison circuit 32, a third comparison circuit 33, a logic processing circuit 34, transistors 12 and 13 for output, and an output terminal Vout. The bridge circuit 10 configures a sensor that detects magnetic field strength, and includes two magnetic reluctance elements 21a and 21b serving as a magneto-electric transducer. As described above, in the bridge circuit 10, the resistance values of the magnetic reluctance elements 21a and 21b change according to the displacement of the magnetic moving member 3, resulting in the variation in the voltage of a detection signal C of the bridge circuit 10.
The detection signal C of the bridge circuit 10 is input to the first comparison circuit 31 and the second comparison circuit 32, and is also input to the third comparison circuit 33 through a high-pass filter including a capacitor 22 and a resistor 23.
The first comparison circuit 31 has a first comparison level VR1, waveform-shapes the amplitude of the detection signal C by DC coupling, and outputs a rectangular wave signal E.
The second comparison circuit 32 has a second comparison level VR2 different from the first comparison level VR1, waveform-shapes the amplitude of the detection signal C by the DC coupling, and outputs a rectangular wave signal F.
The third comparison circuit 33 has a third comparison level VR3 between the first comparison level VR1 and the second comparison level VR2, waveform-shapes the amplitude of the detection signal C after AC coupling, and outputs a rectangular wave signal G.
Hereinafter, the first to third comparison levels VR1 to VR3 will be simply referred to as “comparison levels”, respectively.
The detection signal Cis converted into the rectangular wave signal E through a comparison with the comparison level VR1 in the first comparison circuit 31, and is converted into the rectangular wave signal F through a comparison with the comparison level VR2 in the second comparison circuit 32. Further, the detection signal C is converted into a voltage signal D after the AC processing through the high-pass filter including the capacitor 22 and the resistor 23, and then is converted into the rectangular wave signal G through a comparison with the comparison level VR3 in the third comparison circuit 33.
The output signals E to G of the first to third comparison circuits 31 to 33 are logically processed by the logic processing circuit 34, and then are output as a final output signal K through the transistors 12 and 13.
The logic processing circuit 34 includes a first transistor 41 and a third transistor 43 serially inserted between a supply voltage VCC and a ground, a second transistor 42 and a fourth transistor 44 serially inserted between the supply voltage VCC and the ground, and a fifth transistor 45 inserted between the supply voltage VCC and the ground. The logic processing circuit 34 inputs the output signal of the second transistor 42 to the transistor 12 for output as the final output signal.
Hereinafter, the first to fifth transistors 41 to 45 will be simply referred to as “transistors”, respectively.
The transistor 41 is turned on and off by the output signal E of the first comparison circuit 31, and the transistor 42 is turned on and off by the output signal of the transistor 41. The transistor 43 is serially connected to the transistor 41 and is turned on and off by the output signal G of the third comparison circuit 33. The transistor 45 is turned on and off by the output signal F of the second comparison circuit 32. The transistor 44 is serially connected to the transistor 42 and is turned on and off by the output signal of the transistor 45.
That is, the transistor 41 has an emitter terminal connected to a collector terminal of the transistor 43, a collector terminal (an output terminal) connected to a base terminal of the transistor 42 while being connected to the supply voltage VCC through a resistor, and a base terminal that receives the rectangular wave signal E. Further, the transistor 42 has a base terminal connected to the output terminal of the transistor 41, an emitter terminal connected to the collector terminal of the transistor 44, and a collector terminal (an output terminal) connected to the supply voltage VCC through a resistor and serving as the final output terminal.
In addition, the transistor 45 has an emitter terminal connected to the ground, a collector terminal (an output terminal) connected to a base terminal of the transistor 44 while being connected to the supply voltage VCC through a resistor, and a base terminal that receives the rectangular wave signal F. Moreover, the transistor 44 has an emitter terminal connected to the ground, a collector terminal connected to the emitter terminal of the transistor 42.
In the logic processing circuit 34 having the above configuration, the transistors 41 and 43 configure an inversion input-type AND gate, the transistors 42 and 44 configure an inversion input-type AND gate, and the transistor 45 configures an inverter.
In addition, the transistors 12 and 13 for output configure an amplifier for amplifying the final output signal K.
Accordingly, the final output signal K has a logic level varying depending on the combination of the logic levels of the output signals E to G of the first to third comparison circuits 31 to 33 as shown in (1) to (8) below. Herein, “H” indicates a high level of the rectangular wave signal and “L” indicates a low level of the rectangular wave signal.
(1) when E, G and F are “H, H and H”, K=“H”
(2) when E, G and F are “H, H and L”, K=“H”
(3) when E, G and F are “H, L and H”, K=“H”
(4) when E, G and F are “H, L and L”, K=“L”
(5) when E, G and F are “L, H and H”, K=“H”
(6) when E, G and F are “L, H and L”, K=“L”
(7) when E, G and F are “L, L and H”, K=“H”
(8) when E, G and F are “L, L and L”, K=“L”
FIG. 16 illustrates operation waveforms of signals C′ to G′, and K′ when the magnetic moving member 3 is in a low rotation state, and FIG. 17 illustrates operation waveforms of signals C to G, and K when the magnetic moving member 3 is in a high rotation state.
In the case of the low rotation, single quotes are attached to each signal. That is, the detection signal C becomes C′, the voltage signal D after the AC processing becomes D′, the rectangular wave signal E becomes E′, the rectangular wave signal G becomes G′, the rectangular wave signal F becomes F′, and the final output signal K becomes K′.
In FIG. 16, as apparent from the combination of the voltage level “H and L” of the signals E′, F′, G′ and K′, the rising timing “L→H” of the final output signal K′ at the time of the low rotation is the same as the rising timing of the rectangular wave signal E′ from the first comparison circuit 31.
Further, the falling timing “H→L” of the final output signal K′ is the same as the falling timing of the rectangular wave signal F′ from the second comparison circuit 32.
Meanwhile, in FIG. 17, the rising timing and the falling timing of the final output signal K at the time of the high rotation are the same as the rising timing and the falling timing of the rectangular wave signal G from the third comparison circuit 33, respectively. That is, when the magnetic moving member 3 is in the low rotation state, the output signals E and F after the DC processing from the first comparison circuit 31 and the second comparison circuit 32 are used. When the magnetic moving member 3 is in the high rotation state, the output signal G after the AC processing from the third comparison circuit 33 is used.
At this time, since the phase difference between the rectangular signals E and F after the DC processing from the first comparison circuit 31 and the second comparison circuit 32 and the rectangular signal G after the AC processing from the third comparison circuit 33 is always equal to or less than ¼ period, the final output signal K can be achieved without any difficulty regardless of the rotation states of the magnetic moving member 3. Further, the switching timing of the case of applying the DC processing of the first comparison circuit 31 and the second comparison circuit 32 and the case of applying the AC processing of the third comparison circuit 33 can be arbitrarily set by adjusting the circuit constant of the capacitor 22 and the resistor 23 constituting the high-pass filter.
However, in the conventional apparatus disclosed in JP-A-2007-192733 as described above, as shown in FIG. 18, when the detection signal C is shifted upward and exceeds the comparison level VR2, the rising timing of the final output signal K is the same as the rising timing of the rectangular wave signal E from the first comparison circuit 31. Further, the falling timing of the final output signal K is the same as the falling timing of the rectangular wave signal G from the third comparison circuit 33.
Therefore, in the conventional magnetic detection apparatus as shown in FIG. 18, when the shift amount of the detection signal C is large, it may be difficult to determine setting values of the comparison levels VR1 to VR3 and to detect the accurate position of an object to be detected.